`timescale 1ns / 1ns
/***************************************************************
 * Copyright(C), 2022 蓝萌电子 All Rights Reserved.
 * ModuleName : led.v 
 * Date       : 2022年6月9日
 * Time       : 0:28:05
 * Author     : 沈玲玲
 * Version    : V1.0
 *      Version | Modify
 *      ----------------------------------
 *       v1.0    .....
 *   * Copyright: 2022 蓝萌电子 All Rights Reserved.
 *   *  
 *   * This software is licensed under terms that can be found in the LICENSE file
 *   * in the root directory of this software component.
 *   * If no LICENSE file comes with this software, it is provided GPL3.0.
 *   *  
 *   * Description:
 ***************************************************************/



module led
(
    input [7:0] input_led,
    output reg [7:0] output_led,
    input sys_clk,
    input sys_rst_n
);

reg        led_en_d0; 
reg       led_en_d1;  

wire   en_flag;
//捕获uart_en上升沿，得到一个时钟周期的脉冲信号
assign en_flag = (~led_en_d1) & led_en_d0;

//对led延迟两个时钟周期
always @(posedge sys_clk or negedge sys_rst_n) begin         
    if (!sys_rst_n) begin
        led_en_d0 <= 1'b0;                                  
        led_en_d1 <= 1'b0;
    end                                                      
    else begin                                                                            
        led_en_d1 <= led_en_d0;                            
    end
end


always @ (posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n) begin
        output_led  <= 8'b1111_1111;
    end
    else  begin
        output_led <=  ~input_led;
    end
end


endmodule
